摘要: Charge sensitive amplifiers for fast timing in delay-line readout of parallel plate avalanche counter (PPAC) array are designed. In total, 32 channels are realized on a single printed circuit board with operational amplifiers and other discrete components. Each channel is composed of an integrator, a pole-zero cancelation net, and a linear amplification stage, which can be accommodated to either positive or negative input signals. The design procedure is described in detail. The amplifier performance is calibrated with a signal generator. The gain approximately reaches #6;3 mV/fC with an RMS noise level of around 6 mV. In the application to a prototype PPAC, the amplifiers exhibit good practicality and stability.
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来自：
张月昭
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分类：
核科学技术
>>
核科学与技术
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投稿状态：
已投稿期刊
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引用：
ChinaXiv:202502.00120
(或此版本
ChinaXiv:202502.00120V1)
DOI:10.12074/202502.00120
CSTR:32003.36.ChinaXiv.202502.00120
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科创链TXID：
1f52d9d4-31e2-41dd-9f4a-d0824e6c91fb
- 推荐引用方式：
Yue-Zhao Zhang,Peng Ma,Zhuang-Yu Lin,Zhen-Fei Tan,Xing-Chi Han,Chen Liu,Shuo Wang,Da-Peng Sun,Zhi-Quan Li,En-Hong Wang,Shou-Yu Wang.A 32-channel charge sensitive amplifier for delay-line readout of parallel plate avalanche counter array.null.[DOI:10.12074/202502.00120]
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