A 32-channel charge sensitive amplifier for delay-line readout of parallel plate avalanche counter array

Abstract: Charge sensitive amplifiers for fast timing in delay-line readout of parallel plate avalanche counter (PPAC) array are designed. In total, 32 channels are realized on a single printed circuit board with operational amplifiers and other discrete components. Each channel is composed of an integrator, a pole-zero cancelation net, and a linear amplification stage, which can be accommodated to either positive or negative input signals. The design procedure is described in detail. The amplifier performance is calibrated with a signal generator. The gain approximately reaches #6;3 mV/fC with an RMS noise level of around 6 mV. In the application to a prototype PPAC, the amplifiers exhibit good practicality and stability.